Boolean Logic
Boolean Algebra Fundamentals
Boolean algebra is a branch of mathematics that operates on binary values: 1 (true) and 0 (false). It provides the formal foundation for digital circuit design. Every Boolean expression evaluates to exactly one of these two values, and every Boolean function can be expressed, simplified, and implemented using a finite set of operators.
The three fundamental operators are AND, OR, and NOT. From these three, all other Boolean operators can be derived. NAND and NOR are called universal gates because either one alone is sufficient to construct any Boolean function. XOR and XNOR are useful for parity and comparison operations.
Basic Operators
AND (conjunction): The output is 1 only when all inputs are 1.
A | B | A AND B |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
Notation: , ,
OR (disjunction): The output is 1 when at least one input is 1.
A | B | A OR B |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |
Notation: ,
NOT (negation): The output is the complement of the input.
A | NOT A |
|---|---|
| 0 | 1 |
| 1 | 0 |
Notation: , ,
NAND: The negation of AND. Output is 0 only when all inputs are 1.
A | B | A NAND B |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Notation: ,
NOR: The negation of OR. Output is 1 only when all inputs are 0.
A | B | A NOR B |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 0 |
Notation: ,
XOR (exclusive OR): The output is 1 when inputs are different.
A | B | A XOR B |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Notation: ,
XNOR (exclusive NOR): The negation of XOR. Output is 1 when inputs are the same.
A | B | A XNOR B |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
Notation: ,
Derived Expressions for XOR and XNOR
XOR and XNOR can be expressed entirely in terms of AND, OR, and NOT:
These identities are essential when simplifying expressions that contain XOR/XNOR into standard forms suitable for implementation with basic gates or Karnaugh maps.
Worked Example: Constructing a Truth Table
Construct the truth table for .
Solution
Build column by column, evaluating each sub-expression:
A | B | C | |||
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 1 | 0 |
| 0 | 0 | 1 | 0 | 0 | 0 |
| 0 | 1 | 0 | 1 | 1 | 1 |
| 0 | 1 | 1 | 1 | 0 | 0 |
| 1 | 0 | 0 | 1 | 1 | 1 |
| 1 | 0 | 1 | 1 | 0 | 0 |
| 1 | 1 | 0 | 1 | 1 | 1 |
| 1 | 1 | 1 | 1 | 0 | 0 |
Minterms (where ): , , .
SOP expression:
This can be simplified: (which is the original expression, confirming our truth table is correct). Further simplification: the three minterms share , and the OR of the other terms is , so .
Truth Tables for Multiple Variables
Three-Variable Truth Tables
A three-variable expression has rows. The convention is to list combinations in binary
counting order. For variables A, B, C:
A | B | C | A AND B AND C | A OR B OR C |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 | 1 |
| 0 | 1 | 0 | 0 | 1 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 0 | 1 |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 1 |
Four-Variable Truth Tables
A four-variable expression has rows. The standard ordering assigns the leftmost variable
as the most significant bit. For variables A, B, C, D:
A | B | C | D | A AND B AND C AND D | A OR B OR C OR D |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 1 | 0 | 1 |
| 0 | 0 | 1 | 0 | 0 | 1 |
| 0 | 0 | 1 | 1 | 0 | 1 |
| 0 | 1 | 0 | 0 | 0 | 1 |
| 0 | 1 | 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | 0 | 0 | 1 |
| 0 | 1 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 0 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 | 1 |
| 1 | 0 | 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 1 | 0 | 1 |
| 1 | 1 | 0 | 0 | 0 | 1 |
| 1 | 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 1 | 1 |
Constructing Truth Tables for Arbitrary Expressions
Given an expression, construct the truth table by evaluating each sub-expression column by column.
Worked example: Construct the truth table for
A | B | C | |||||
|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
| 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 | 1 | 0 | 1 | 1 |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 |
| 1 | 0 | 1 | 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
| 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 |
The minterms (rows where ) are: , , , .
Boolean Identities and Laws
The following identities are the tools for algebraic simplification. Each identity can be verified by constructing truth tables for both sides and confirming they are identical.
Fundamental Identities
| Identity | AND Form | OR Form |
|---|---|---|
| Identity | ||
| Null (Domination) | ||
| Complement | ||
| Idempotent | ||
| Commutative | ||
| Associative | ||
| Distributive | ||
| Absorption | ||
| Double Negation |
De Morgan's Laws
De Morgan's Laws are the most frequently applied identities in Boolean simplification. They allow the distribution of a NOT over an AND or OR:
For three variables, De Morgan's Laws extend as:
The general rule: invert each variable, and swap AND with OR (or vice versa).
Worked Example: Applying De Morgan's Laws
Simplify using De Morgan's Laws.
Solution
Step 1: Apply De Morgan's to the outer NOT (treating as the inner expression):
Step 2: Apply De Morgan's to each remaining term:
Step 3: Apply the distributive law:
Step 4: Simplify using idempotent law () and commutative:
Step 5: Apply absorption ():
Step 6: Apply absorption again ():
The simplified expression requires 1 NOT, 1 AND, and 1 OR gate (3 gates total), compared to the original which requires 2 AND, 1 OR, and 1 NOT (4 gates total) -- or more if not shared.
Consensus Theorem
The term is redundant because it is the "consensus" of the other two terms. The variable appears in the first term and does not; appears in the second term and does not. The consensus term is .
The dual form is:
Simplifying Boolean Expressions
Simplification reduces the number of gates and inputs required, which reduces cost, propagation delay, and power consumption. The approach is systematic: apply identities one at a time, justifying each step.
Worked Example 1
Simplify:
Step 1: Factor from the first two terms (distributive law, reverse):
Step 2: Apply complement law:
Step 3: Apply identity law:
Step 4: Apply absorption:
Worked Example 2
Simplify:
Step 1: Group terms containing :
Step 2: Recognize that (XNOR):
This is a valid simplification but not in sum-of-products form. For circuit implementation, we can expand:
Using absorption, the term absorbs both and . We already have , so is generated when we expand :
So the full SOP is:
This simplifies to , which requires only 4 gate inputs instead of the original 8.
Worked Example 3 (Using De Morgan's Laws)
Simplify:
Step 1: Apply De Morgan's Law to the outer NOT:
Step 2: Apply De Morgan's Law to each term:
This is (XNOR). The expression is now in minimal SOP form.
Logic Gates
Gate Symbols and Expressions
| Gate | Boolean Expression | Standard Symbol (ANSI) | IEC Symbol |
|---|---|---|---|
| AND | D-shaped output | & | |
| OR | Curved output | >=1 | |
| NOT | Triangle with bubble | 1 (with o) | |
| NAND | AND with bubble | & (with o) | |
| NOR | OR with bubble | >=1 (with o) | |
| XOR | OR with extra curve | =1 | |
| XNOR | XOR with bubble | =1 (with o) |
NAND as a Universal Gate
NAND alone can implement all other gates:
- NOT: Connect both inputs of NAND to the same signal:
- AND: NAND followed by NOT:
- OR: Use De Morgan's: . Feed and (each from a NAND-as-NOT) into a NAND gate.
NAND-NAND implementation of :
Apply De Morgan's in reverse:
This requires two NAND gates for and , and a third NAND gate to combine them. Total: 3 NAND gates.
Worked Example: Implementing a Function with NAND Gates Only
Implement using only NAND gates.
Solution
Step 1: Convert to NAND-NAND form. We need the expression in the form where and are themselves NAND expressions.
The SOP form is . Apply De Morgan's in reverse:
Step 2: Verify: . Correct.
Step 3: Implement:
- NAND gate 1: inputs → output
- NAND gate 2 (as NOT): inputs → output (Wait, we do not need this -- the final NAND gate handles the OR.)
Actually, the expression needs . To get from a NAND gate: NAND gate 2: inputs → output .
- NAND gate 1: inputs →
- NAND gate 2: inputs →
- NAND gate 3: inputs →
Total: 3 NAND gates.
NOR as a Universal Gate
NOR alone can implement all other gates:
- NOT: Connect both inputs to the same signal:
- OR: NOR followed by NOT:
- AND: Use De Morgan's: . Feed and (each from a NOR-as-NOT) into a NOR gate.
Karnaugh Maps (K-Maps)
Karnaugh maps provide a visual method for minimizing Boolean expressions with up to 4 variables. They eliminate the need for trial-and-error algebraic manipulation by systematically identifying groups of adjacent 1s (or 0s).
The Adjacency Principle
Two minterms are adjacent if they differ in exactly one variable. Adjacent minterms can be combined by eliminating the variable that changes. In a K-map, adjacency wraps around the edges (the top row is adjacent to the bottom row; the leftmost column is adjacent to the rightmost column).
2-Variable K-Map
A 2-variable K-map has cells. The columns represent one variable and the rows represent the other.
Worked example: Minimize
B = 0 | B = 1 | |
|---|---|---|
A=0 | 1 | 1 |
A=1 | 1 | 0 |
The cells for , , and are 1.
Group the two cells in row A=0: this spans both columns, so B is eliminated. This group
represents .
Group the two cells in column B=0: this spans both rows, so A is eliminated. This group
represents .
Result:
Verify: The three minterms by absorption. Correct.
3-Variable K-Map
A 3-variable K-map has cells. The standard layout uses Gray code ordering (00, 01, 11, 10)
so that adjacent columns differ by exactly one bit. Variables B and C are the column headers;
A is the row header.
Worked example: Minimize
The minterms are: , , , , , .
BC = 00 | BC = 01 | BC = 11 | BC = 10 | |
|---|---|---|---|---|
A=0 | 1 | 1 | 0 | 1 |
A=1 | 0 | 1 | 1 | 1 |
Step 1: Identify groups.
- Group 1: Cells and -- adjacent horizontally. These are
and . The variable that changes
is
C, so eliminate it: . - Group 2: Cells , , -- all three in row
A=1. But and are adjacent, and and are adjacent. Group and : these are and , eliminatingC: . - Group 3: Cells and -- adjacent vertically. These are
and , eliminating
A: . - Group 4: Cells and -- adjacent vertically. These are and
, eliminating
A: .
Now apply the covering rule: every 1 must be covered by at least one group.
Optimal grouping:
- : covers
- : covers
- : covers
- : covers
But is only covered by , so that group is essential. is only covered by , so that is essential. is only covered by , so that is essential. is only covered by , so that is essential.
4-Variable K-Map
A 4-variable K-map has cells. The row headers (AB) and column headers (CD) both use
Gray code ordering: 00, 01, 11, 10.
Worked example: Minimize
CD = 00 | CD = 01 | CD = 11 | CD = 10 | |
|---|---|---|---|---|
AB=00 | 1 | 1 | 0 | 1 |
AB=01 | 0 | 1 | 0 | 0 |
AB=11 | 0 | 0 | 0 | 0 |
AB=10 | 1 | 1 | 0 | 1 |
Step 1: Identify groups of 1s.
- Group 1: The four corners form a valid group because K-maps wrap around both horizontally and
vertically. Cells , , , are the four corners. In terms of
variables, these are ,
, ,
. Variables
AandCchange, so they are eliminated. Result: . - Group 2: Cells and are adjacent. These are
and .
Variable
Dchanges, so eliminate it: . - Group 3: Cells and are adjacent vertically. These are
and . Variable
Bchanges, so eliminate it: . - Group 4: Cells and are adjacent. These are
and . Variable
Dchanges: .
Step 2: Determine essential prime implicants.
The four-corner group covers .
covers .
Check coverage: covered by , covered by , covered by , covered by , covered by , is NOT covered yet, covered by .
. We need to cover it. Options:
- does not cover it (requires ).
- does not cover it (requires ).
- covers .
- covers but not .
So we add .
This requires three AND gates and one OR gate, for a total of 4 gates with 9 gate inputs.
Worked Example: 3-Variable K-Map with Don't Cares
Minimize where denotes don't care conditions.
Solution
The minterms are . The don't cares are . Place these on the K-map:
BC = 00 | BC = 01 | BC = 11 | BC = 10 | |
|---|---|---|---|---|
A=0 | X | 1 | 1 | 0 |
A=1 | 0 | 1 | 0 | X |
Without don't cares:
- : group vertically → (columns 01 and 11, row A=0)
- : isolated →
(2 terms, 5 literals)
With don't cares: Set (X at 0,00) to 1 and (X at 1,10) to 1 to form larger groups.
- Group and : if X=1, this gives
- Group and : gives
- Group and : gives
- Group : if X=1, can pair with ? No, . Can pair with ? No, . So remains isolated as ... but that is a single cell.
Better approach: use and together → (horizontal pair). Then and → (horizontal pair). and → (vertical pair).
Optimal grouping:
- : covers (2 cells)
- : covers (2 cells, overlaps)
But is not covered by . And is not covered by . So we need both. Can we do better with don't cares?
Set to 1: pair → . Set to 1: is isolated.
Try: covers . covers . is not covered yet. We need or for . also covers .
So:
Check coverage: (don't care, covered by ), (covered by all three), (covered by ), (covered by ), (don't care, not covered but that is OK).
Actually, covers and covers . Together they cover all required minterms (). The don't care could be used to replace with , but that only covers , leaving uncovered.
Best result with don't cares: (2 terms, 3 literals). Wait, let me check: .
Check: (): . Yes. (): . Yes. (): . Yes.
Wait, that is wrong. when : . Correct. when : . Correct.
So = .
This covers with only 2 terms and 3 literals. No don't cares were even needed for this simplification -- the expression was already optimizable. But don't cares give us additional flexibility if we needed to cover or .
Final answer: (implemented as 2 NOT gates, 2 AND gates, 1 OR gate = 5 gates, or using NAND-NAND: 4 NAND gates).
K-Map Grouping Rules
- Groups must be rectangular (or square) and contain cells (1, 2, 4, 8, or 16).
- Groups must be as large as possible. A group of 4 is better than two groups of 2.
- Every 1 in the map must be covered by at least one group.
- Groups can wrap around the edges (top-bottom, left-right).
- Overlapping groups are allowed and often necessary.
- The four corners of a 4-variable map form a valid group.
Product-of-Sums (POS) via K-Maps
To obtain the POS form, group the 0s instead of the 1s, then apply De Morgan's Law to the result.
Worked example: Using the same map as the 4-variable example above, group the 0s.
The 0s are at: .
This produces a POS expression. However, since there are more 0s than 1s in this case, the SOP form is simpler. POS is advantageous when there are fewer 0s than 1s.
Don't Care Conditions
Don't care conditions arise when certain input combinations can never occur or when the output value
for certain inputs is irrelevant. In K-maps, don't cares are marked with X and can be treated as
either 0 or 1, whichever produces a simpler expression.
Worked example: A circuit has inputs A, B, C where the input combination
A = 1, B = 1, C = 1 is impossible. The required outputs for the other 7 combinations are:
A | B | C | F |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 0 |
| 1 | 1 | 1 | X |
The K-map is:
BC = 00 | BC = 01 | BC = 11 | BC = 10 | |
|---|---|---|---|---|
A=0 | 0 | 1 | 1 | 0 |
A=1 | 1 | 1 | X | 0 |
Without don't cares, the optimal SOP is:
- : (group vertically in columns 01 and 11 of row
A=0) - : (row
A=1, columns 00 and 01)
With don't cares, we can set the X to 1 to create a larger group:
- Cells , , , : if X = 1, this is a group spanning both
rows and columns 01 and 11. Variables
AandBchange, so eliminate them: . - Cells and : .
But wait -- and . The group covers these. The group covering columns 01 and 11 gives . Together: .
Check: . For : (correct). For : (correct). For : (correct). The don't care () gives , which is acceptable since the output is irrelevant for this input.
The expression (2 terms, 3 literals) is simpler than (2 terms, 4 literals).
Converting Between Representations
Boolean Expression to Truth Table
Given any Boolean expression, evaluate it for every combination of input values. For an expression with variables, construct rows and evaluate the expression for each.
Truth Table to Boolean Expression (SOP)
- Identify all rows where the output is 1.
- For each such row, write a minterm: AND together each variable (complemented if 0, uncomplemented if 1).
- OR together all minterms.
Truth Table to Boolean Expression (POS)
- Identify all rows where the output is 0.
- For each such row, write a maxterm: OR together each variable (complemented if 1, uncomplemented if 0).
- AND together all maxterms.
Boolean Expression to Logic Circuit
Replace each operation with its corresponding gate:
- AND operations become AND gates
- OR operations become OR gates
- NOT operations become NOT gates (inverter bubbles)
The structure of the expression dictates the circuit topology. An SOP expression produces a two-level circuit: AND gates feeding into an OR gate.
Logic Circuit to Boolean Expression
Trace the circuit from inputs to outputs:
- Label each gate output with the expression it computes.
- Work from left to right (inputs to outputs).
- The final gate output is the overall expression.
Worked example: A circuit has inputs A, B, C. An AND gate takes A and B. An OR gate
takes the AND gate output and C. The final expression is .
Half Adder and Full Adder
Half Adder
A half adder adds two single-bit numbers and produces a sum and a carry. It does not accept a carry-in from a previous stage.
A | B | Sum | Carry |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
The sum bit follows the XOR pattern:
The carry bit follows the AND pattern:
Circuit implementation: One XOR gate and one AND gate.
Full Adder
A full adder adds two single-bit numbers plus a carry-in from a previous stage, producing a sum and a carry-out.
A | B | Sum | ||
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 1 |
Sum derivation via K-map:
A=0 | 0 | 1 | 0 | 1 |
A=1 | 1 | 0 | 1 | 0 |
The 1s appear at , , , . No two adjacent 1s share a common group in the standard sense. Each 1 is isolated (adjacent cells are 0). Therefore, no simplification is possible, and the SOP form is the sum of minterms:
Carry-out derivation via K-map:
A=0 | 0 | 0 | 1 | 0 |
A=1 | 0 | 1 | 1 | 1 |
Groups:
- : row
A=1, columns 01, 11, 10. This is (column 00 is excluded). The group spanning and gives , and the group spanning and gives . - : column 11, both rows. This is .
Alternative carry expression:
This form has significance: it shows that a full adder can be constructed from two half adders. The first half adder computes (partial sum) and (partial carry). The second half adder adds the partial sum and to get the final sum, and the final carry is the OR of the partial carry and the carry from the second half adder.
Worked Example: Building a Circuit from a Truth Table
A voting system has three inputs (A, B, C -- each person votes yes=1 or no=0). The output is 1 if a majority votes yes (2 or 3 yes votes). Derive the Boolean expression and count the gates needed.
Solution
Step 1: Truth table
A | B | C | F (majority) |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 1 |
Step 2: K-map
BC = 00 | BC = 01 | BC = 11 | BC = 10 | |
|---|---|---|---|---|
A=0 | 0 | 0 | 1 | 0 |
A=1 | 0 | 1 | 1 | 1 |
Step 3: Group
- and : vertical pair →
- and : horizontal pair →
- and : horizontal pair →
Essential prime implicants: , , (each covers a minterm that no other group covers: only by , only by , only by ).
Step 4: Gate count
- 3 AND gates (2-input each)
- 1 OR gate (3-input)
- Total: 4 gates
Alternative implementation using XOR:
This uses 1 XOR gate, 2 AND gates, 1 OR gate = 4 gates (same count, but uses XOR which may be cheaper in some implementations).
Ripple Carry Adder
A ripple carry adder chains multiple full adders to add multi-bit numbers. The carry-out of each stage feeds into the carry-in of the next stage. For an -bit adder, full adders are required.
The main disadvantage is propagation delay: the carry must ripple through all stages sequentially. The worst-case delay is , where is the carry propagation time of a single full adder.
Common Pitfalls
Forgetting to Apply De Morgan's Correctly
The most common error is distributing the NOT incorrectly. De Morgan's Laws invert each variable AND swap the operator. A typical mistake:
The correct application is:
Incomplete K-Map Grouping
Failing to identify all possible groups, particularly wrap-around groups, leads to non-minimal expressions. Always check:
- Top and bottom rows for horizontal adjacency
- Left and right columns for vertical adjacency
- The four corners as a valid group
- Groups of 4 before groups of 2 (larger groups eliminate more variables)
Missing Essential Prime Implicants
An essential prime implicant is a group that covers at least one minterm not covered by any other group. If you fail to include all essential prime implicants, the expression will not correctly represent the function. Always identify essential prime implicants first, then cover any remaining uncovered minterms with the largest possible groups.
Confusing SOP and POS
Sum-of-products (SOP) is an OR of ANDs. Product-of-sums (POS) is an AND of ORs. When converting from a truth table, SOP is obtained from the 1s and POS from the 0s. Mixing these up produces an incorrect expression.
Ignoring Don't Care Conditions
Don't care conditions provide additional flexibility for simplification. Setting a don't care to 0 when it should be 1 (or vice versa) may prevent the formation of a larger group, resulting in a non-minimal expression. Always consider both options for each don't care and choose the one that maximizes group sizes.
Incorrect Gate Counting
When implementing a circuit, count the actual number of physical gates required. An XOR gate is a single gate, not two gates (even though it can be expressed as ). A NAND gate is a single gate, not an AND gate followed by a NOT gate. Physical gate count determines circuit cost and delay.
Problem Set
Problem 1: Construct the truth table for and identify what logic gate this is equivalent to.
Solution
A | B | |||||
|---|---|---|---|---|---|---|
| 0 | 0 | 1 | 1 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 |
when . This is the XOR gate: .
If you get this wrong, revise: Basic Operators
Problem 2: Apply De Morgan's Laws to simplify .
Solution
Step 1: Apply De Morgan's to the outer NOT:
Step 2: Apply De Morgan's to :
Result:
Verify with : LHS . RHS . Match.
Verify with : LHS . RHS . Match.
If you get this wrong, revise: De Morgan's Laws
Problem 3: Simplify using Boolean algebra identities.
Solution
Step 1: Apply absorption repeatedly. (absorption):
Step 2: Apply absorption again:
Step 3: Apply absorption one more time:
Every term contains as a factor, so absorbs all of them. The entire expression simplifies to just .
If you get this wrong, revise: Boolean Identities
Problem 4: Minimize using a 3-variable K-map.
Solution
Place minterms on the K-map:
BC = 00 | BC = 01 | BC = 11 | BC = 10 | |
|---|---|---|---|---|
A=0 | 0 | 0 | 1 | 1 |
A=1 | 0 | 1 | 1 | 1 |
Identify groups:
- : square → (columns 10 and 11, variable B is eliminated; both rows, variable A is eliminated)
- : three cells in row A=1 → not a valid group (must be power of 2). Instead: → , and →
But the group already covers . The only uncovered minterm is .
. Group with → . Or group with → .
Best option: covers and also covers (which is 0, so no harm).
Wait -- check: does match all minterms? (): . But should be 1! So .
The group spanning columns 10 and 11 gives ? No. Columns 10 (BC=10) and 11 (BC=11): variable B changes. So the group gives for row A=1... wait, I need to think more carefully.
The square covers cells . In row A=0, columns 10 and 11: and → eliminates C → . In row A=1: and → . Together: .
So the group gives , not .
Remaining: . Group with : .
By absorption: .
Final answer:
Verify: (): . Correct. (): . Correct. (): . Correct.
If you get this wrong, revise: 3-Variable K-Maps
Problem 5: Convert the following truth table to both SOP and POS form:
A | B | F |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
Solution
SOP form (from the 1s -- rows 00 and 11):
This is XNOR: .
POS form (from the 0s -- rows 01 and 10):
Maxterm for row 01 (): Maxterm for row 10 ():
Verification: Expand the POS: . This matches the SOP. Both are correct.
If you get this wrong, revise: Converting Between Representations
Problem 6: A 4-variable K-map has 1s at positions . All other positions are 0. What is the minimized expression?
Solution
CD = 00 | CD = 01 | CD = 11 | CD = 10 | |
|---|---|---|---|---|
AB=00 | 1 | 0 | 0 | 1 |
AB=01 | 0 | 0 | 0 | 0 |
AB=11 | 0 | 0 | 0 | 0 |
AB=10 | 1 | 0 | 0 | 1 |
The four 1s are at the four corners: . The four corners form a valid group because K-maps wrap around both edges.
The four corners have: A varies (0 and 1), C varies (0 and 1), but B=0 and D=0 in all four.
This is the classic "four corners" grouping. The expression requires only 2 NOT gates and 1 AND gate = 3 gates.
If you get this wrong, revise: 4-Variable K-Maps
Problem 7: Using only NAND gates, implement the NOT function, the AND function, and the OR function. Show the gate connections.
Solution
NOT from NAND: Connect both inputs to the same signal.
1 NAND gate.
AND from NAND: NAND followed by NOT (NAND-as-NOT).
2 NAND gates.
OR from NAND: Use De Morgan's:
- NAND gate 1: inputs → (NOT)
- NAND gate 2: inputs → (NOT)
- NAND gate 3: inputs →
3 NAND gates.
If you get this wrong, revise: NAND as Universal Gate
Problem 8: For the majority voting circuit , determine the output when: (a) A=1, B=1, C=0 (b) A=0, B=1, C=1 (c) A=0, B=0, C=1
Solution
(a) (majority: 2 out of 3 yes)
(b) (majority: 2 out of 3 yes)
(c) (minority: 1 out of 3 yes)
The output is 1 whenever at least two inputs are 1.
If you get this wrong, revise: Boolean Algebra Fundamentals
Problem 9: A student writes: . Is this correct? If not, find and fix the error.
Solution
This is incorrect. The student applied De Morgan's only to but not to the entire expression.
Correct application:
Verify with :
- LHS:
- Student's answer: (wrong!)
- Correct answer: (correct!)
If you get this wrong, revise: De Morgan's Laws and Common Pitfalls
Problem 10: Explain why the consensus theorem allows the term to be removed from . Verify by checking all 8 input combinations.
Solution
The consensus theorem states: .
The term is redundant because whenever (meaning and ), either (making ) or (making ). So always coincides with at least one of the other terms being 1.
Verification:
A | B | C | |||||
|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
| 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 |
| 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 |
The last two columns are identical for all 8 rows, confirming that is indeed redundant.
If you get this wrong, revise: Consensus Theorem
Problem 11: Design a half subtractor. It has inputs A (minuend) and B (subtrahend), and outputs Diff (difference) and Borrow. Construct the truth table, derive Boolean expressions, and identify the gates needed.
Solution
Truth table (binary subtraction: , , , with borrow):
A | B | Diff | Borrow |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 |
Diff: 1 when inputs differ → XOR:
Borrow: 1 only when →
Gates needed:
- 1 XOR gate (for Diff)
- 1 NOT gate (for )
- 1 AND gate (for )
- Total: 3 gates
If you get this wrong, revise: Half Adder
Problem 12: Given , use a K-map to find the minimal SOP expression.
Solution
BC = 00 | BC = 01 | BC = 11 | BC = 10 | |
|---|---|---|---|---|
A=0 | 1 | 0 | 0 | 1 |
A=1 | 1 | 0 | 1 | 1 |
Groups:
- : four corners (wrap-around ) → (A and B both vary; C=0 in all four)
- : horizontal pair →
Check coverage: (), (), (), ( and ), (). All covered.
Gates: 1 NOT + 1 AND + 1 OR = 3 gates (or using NAND-NAND: 3 NAND gates).
If you get this wrong, revise: 4-Variable K-Maps and K-Map Grouping Rules